Yield Prediction of Operational Amplifiers within the ACACIA Framework

In recent years, Analog design tools have helped reduce the design time for different kinds of custom analog circuits. One such tool, the CMU Analog Design System, ACACIA, can synthesize and layout various analog circuits, in about 10 minutes. Due to the strong correlation between yield and profitability, it is important to predict the design yield, and attempt to change the design to improve the yield. Currently, yield prediction strategies involve the use of SPICE-type simulators in a Monte Carlo analysis, taking significant computation time. We propose a macromodel based approach to rapidly estimate parametric yield. In such an approach, the computation time is drastically reduced, making it possible for the designer to explore design tradeoffs for yield enhancement. Acknowledgements First, I would like to thank my advisor, L. Richard Carley, for his guidance throughout the development of this project. I would also like to thank Rob Rutenbar for his helpful comments. The CMU Analog Group and the CAD center community has provided me with significant support in completing a Masters, and I would like to acknowledge several members who were particularly generous to me with their knowledge and experience: Jay Brockman, Dave Garrod, John Kibarian, Katsufumi Nakamura, Anne Meixner, Emil Ochotta. Finally I would like to thank my family and my friends at Delta Upsilon for their support and encouragement.